Seattle Conference on Scalability: Scalable Multiprocessor Programming via Transactional Memory
As power restrictions have limited performance advances in a single core, new generations of processors are providing a steadily increasing number of cores on a single die. Effectively utilizing such processors requires that programmers write concurrent, scalable programs that typically consist of multiple threads of execution. To communicate between threads, programmers rely on lock-based synchronization to control concurrent access to shared data. Locks are notoriously difficult to use: they do not compose well, they can lead to deadlock, and they must used in fine-grain manner to achieve good scalability.
Transactional memory (TM) offers a promising alternative that avoids many of the hazards of locks. At a semantic level, TM provides stronger guarantees of atomicity and isolation across multiple threads. At an implementation level, TM enables greater scalability via optimistic concurrency techniques. In this talk, I will provide a survey of transactional memory and discuss the opportunities and challenges to providing it in future production environments.
Speaker: Vijay Menon
Vijay Menon is a member of the technical staff at Google working on programming systems infrastructure. His primary areas of interest include programming languages, compilers, managed runtimes, and parallel computing. Vijay holds a Ph.D. in Computer Science from Cornell University and a B.S. in Electrical Engineering and Computer Science from the University of California at Berkeley. Prior to Google, Vijay was a senior research scientist in the Programming Systems Lab at Intel. He has published over 15 articles in premier programming language and parallel computing conferences and journals.
Slides for this talk are available at http://groups.google.com/group/seattle-scalability-conference
Google Tech Talks
June 14, 2008