Engineering a Fast PCIe-Attached Storage Array for Next-Generation Non-Volatile Memories
Google Tech Talk
December 13, 2010
Presented by Steven Swanson.
Fast non-volatile memories with performance comparable to DRAM (whether it is PCM, the Memristor, scalable MRAM, or something else) will be upon us in a few short years. These technologies are around 10,000 times faster than spinning disks and 1000 times faster than flash in terms of latency, and they offer enormous gains in bandwidth as well. Fully leveraging these technologies will require far-reaching changes in the way that programmers use and reason about persistent data and how systems manage persistent storage. I will describe a prototype high-performance storage system called Moneta that we have developed in the Non-Volatile Systems Laboratory at UCSD. Moneta provides a window into the future storage systems by using DRAM to emulate advanced non-volatile memories. In building Moneta, we have found that existing system and application software designed for a world of slow disks is a poor fit for fast devices like Moneta. In response, we have co-designed the Moneta hardware interface and the Moneta driver to increase bandwidth by over 10x for small requests, reduce latency to just 12us for 4KB accesses, and allow Moneta to sustain 1.1 Million IOPS. We compare Moneta to a range of storage devices based on disks, flash, and advanced non-volatile memories, and find that leveraging the speed of fast non-volatile memories will require significant changes in file systems and applications.
Bio: Steven Swanson is an assistant professor in the Department of Computer Science and Engineering at the University of California, San Diego and the director of the Non-volatile Systems Laboratory. His research interests include the systems, architecture, security, and reliability issues surrounding non-volatile, solid-state memories. He also co-leads projects to develop low-power co-processors for irregular, mobile applications (e.g., Android Apps) and to devise software techniques for using multiple processors to speed up single-threaded computations. In previous lives he has also worked on scalable dataflow architectures, ubiquitous computing, and simultaneous multithreading. He received his PhD from the University of Washington in 2006.